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Press Box

Welcome to the Cadence Europe Press Box. These pages contain up-to-date press information and resources for journalists in Europe

For more press information, please see the Contacts page.

January 2007

Ubicom Chooses Cadence Incisive Formal Verifier for Logic Design Team Verification

December 2006

Cadence Incisive Formal Verifier Helps UPEK Improve Design Team Productivity

Cadence Encounter RTL Compiler Extends Technology Lead in Synthesis, Increases Quality of Silicon

New Cadence Virtuoso Custom Design Platform Features TSMC 90-Nanometer RF Process Design Kit

Wipro Selects Cadence as Primary Vendor for VLSI and System Design Solutions

MegaChips LSI Solutions Adopts Incisive Xtreme to Improve Design Team Verification Process

Cadence and Advantest Address Zero-Defect Testing Requirements for Automotive Electronics

Incisive Palladium III Productivity Enables High Performance Enterprise System-Level Verification

Cadence Enterprise System-Level Verification Enables Predictable Software, Hardware and System Quality

Common Power Format Contributed by Cadence to SI2 Ahead of Schedule as a Result of Significant Customer Input

November 2006

Cadence strengthens Verification Alliance program in India by adding 13 new partners

Momentum builds for Cadence VoltageStorm with Dynamic Power Analysis

Sirific Wireless readies two 3.5G RF transceivers for market using Cadence Logic Design technology

Cadence Announces winners of the Collaborations Award for Excellence in Advancing Design Chain Alliances

Cadence Aligns with IBM to Accelerate ASIC Design with Cadence Logic-Design Team Technology

Cadence Behind Success of national 863 Program's Godson 2E Processor

Cadence and SMIC Collaborate to Address Wireless Design Challenges in China

GUC Tapes Out Five 90-Nanometer Chips with Cadence Encounter Synthesis and Implementation

Cadence and UMC Collaborate to Achieve Wireless Reference Design Silicon Success for Customers

Six New IP Providers Join Cadence OpenChoice; Expand IP Program to Enhance the Design Chain Ecosystem

Cadence and Si2 Collaboration Paves the Way to a Unified Low-Power Standard

October 2006

Freescale Continues Successful Migration to Cadence Encounter Test

Cadence Reports Q3 Revenue Up 9% Over Q3 2005

Cadence Expands Design Chain Through Encounter Test Collaboration with Source III

Azul Systems Adds Cadence Encounter Test to Its Design and Manufacturing Test Flow

ARM and Cadence Collaborate on Testability Requirements of ARM Partners with Encounter Test

NEC Improves Product Quality; Lowers Manufacturing Costs with Cadence Encounter Test

Cadence Logic Design Team Solution Addresses Front-End Design 'Predictability Crisis'

Redback Networks Selects Cadence Xtreme III System for Its Most Challenging Verification Tests

SI2's Low-Power Coalition to Have Access to Common Power Format

Cadence Develops Lithography-Aware Design Flow in Collaboration with Brion and Clear Shape

September 2006

Cadence Announces Availability of Design-In IP Portfolio for Memory Designs

Cadence Removes Design Team Barriers for Broad Deployment of Hardware Assisted Verification

Amkor Selects Cadence Technologies for SiP Design Centers Worldwide

Cadence Reinvents Virtuoso Platform for New Generations of Complex Custom IC Designs

Cadence and SMIC Deliver 90-Nanometer Low-Power Solution for Energy-Efficient SoCs

Fujitsu Delivers ARM9E Processors for ASIC Designs Using Cadence Encounter RTL Compiler

Fujitsu Adopts Cadence Encounter Timing System for Signoff Timing Analysis

Cadence Announces Encounter Timing System for Advanced Timing Signoff Analysis

Power Forward Initiative Broadens Industry Support, Accelerates Standardization of Common Power Format

August 2006

Toshiba Adopts Cadence QRC Extraction for 65-nm Design Flows

Realtek and Cadence Address Verification with Cadence Encounter Conformal Technologies

Cadence Introduces Universal Verification Components

July 2006

Siemens Expands its Use of Cadence Incisive Formal Verifier to Improve Time to Market

Amalfi Semiconductor Turns to Cadence Kit to Speed Up Product Development for Cell Phones

Cadence Reports Q2 Revenue Up 12% Over Q2 2005

Cadence, Magma, and Extreme DA Collaborate to Develop Industry Standard Library Format for Statistical Analysis Through SI2

Cadence and ARM Introduce First Automated Design and Implementation Flow for the ARM Cortex-A8 Processor

Power Forward Initiative Expands and Invites EDA Companies to Join Advisory Group

Cadence and TSMC Accelerate 65-Nanometer Design with TSMC Reference Flow 7.0

Cadence Extends Test and Yield Diagnostics Technology Lead

OKI Standardizes on the Cadence Incisive Formal Verifier for design team usage

June 2006

Denali's Databahn Memory Controller IP Supports Cadence Encounter Synthesis

Agere Systems Tapes Out Next-Generation, 90-nm Mobile Solution Chip Using Cadence X Architecture

ARC and Cadence Announce Optimized Integration of Encounter� Digital IC Platform with ARChitect Processor Configurator

Cadence Mainstreams System-in-Package Design

Cadence and ARM Deliver Innovative Kit to Speed Verification Closure for ARM Processor-Based Designs

Freescale Tapeout Marks 1,000th Design for Cadence Celtic NDC

Comit Systems Expands Adoption of Cadence Encounter Digital IC Design Technology

Hong Kong's ASTRI Reconfirms Cadence as Key EDA Solutions Provider

Cadence Announces Line-Up for First CDNLive! EMEA User Conference in Nice, France

Cadence Debuts Industry's First Transaction-Based System Verification and Management Solution

May 2006

UMC Announces Readiness for 65-nanometer X Architecture Designs

TSMC Production-Ready for 65-nm X Architecture Designs

Cadence Unites Industry Leaders to Overcome Low-power Barriers for the Electronics Industry

TSMC Adds Cadence Technologies for 65-Nanometer Design

Cadence Releases Proven Reference Methodology for New ARM Cortex-R4 Processor

KPIT Cummins Infosystems Adopts Cadence Analog Mixed Signal Methodology Kit

Fastrack Design Standardizes on Cadence Fire & Ice QX Extraction

April 2006

Cadence Reports Q1 Revenue Up 12% Over Q1 2005

Cadence and PDF Solutions to Collaborate on IC Design-For-Manufacturability Products and Roadmap

Cadence Continues Product-Segmentation Strategy with Allegro Silicon-Package-Board Platform

Cadence Encounter Global Synthesis Supported by STMicroelectronics for Its ASIC Customers

Saifun Semiconductors Adopts Cadence Analog Mixed-Signal Methodology Kit

New Cadence Incisive Enterprise Technology Eases Creation of Verification Scenarios

Cadence Collaborates with IBM to Exceed Testability Goals with Cell Broadband Engine

Agere Systems Standardizes on Cadence Virtuoso and Incisive Palladium Technologies to Speed Time to Market for 90- And 65-Nanometer Semiconductors

Cadence and Teranetics Collaborate on Design of 10 Gigabit Ethernet Chips Using X Architecture

Cadence Virtuoso Platform Speeds Time to Market for Zarlink's Ultra Low-Power SoCs

SMIC and Cadence Deliver New Analog Mixed-Signal Reference Flow to Speed Fabless Chip Design

Cadence Announces Executive and Engineering Fellow Promotions on Back of Strong 2005 Business Performance

March 2006

Renesas Technology Gets Up to 2X Design Productivity Increase with Cadence Virtuoso NeoCircuit

Hitachi Communication Technologies Speeds Time to Market for ASIC Designs with Cadence Synthesis

Cadence Virtuoso Platform Provides 10x Improvement in Verification Time for VIS

Cadence Incisive Xtreme Server Helps Speed Delivery of Sun's Breakthrough Processor Technology

IEEE Recognizes Cadence Leadership and Contributions to IEEE 1800 SystemVerilog Standard

New Cadence 'Knowledge System' Speeds Adoption and Customization of Incisive Plan-to-Closure Methodology

Cadence and CEVA Collaborate to Deliver Verification Process Automation to End Customers

February 2006

Cadence and Moscow Institute of Electronic Technology Conclude Joint Education Project

Silicon Design Chain Validates Enhanced Power Management Methodology with ARM 1136JF-S

Cadence Collaborates with IBM and Chartered to Deliver 90-nm Low-Power, Yield-Aware Reference Flow

Cadence Encounter Platform Speeds Volume Production for STMicroelectronics' HDTV Decoder

Cadence Expands Design for Manufacturing Offering with Solution for Lithography-Aware Design

Cadence Appoints New Vice President of Corporate Marketing

Cadence X Architecture Design Solution Wins 2006 IEC DesignVision Award

Cadence Virtuoso Speeds Design and Verification of Sirific's 3.5G Cellular Transceivers

Cadence Announces Plans for Global Series of Events to Connect With Cadence Users in 2006

Cadence Reports Q4 Revenue Up 10% Over Q4 2004

January 2006

Cadence Unveils Advanced Manufacturing-Aware Chip-Optimization Technology

Fujitsu Deploys 65nm Reference Design Flow Based on Cadence Encounter GXL Technology

VeriSilicon Tapes out Flip-Chip Design With Cadence Encounter

VIA Tapes Out 90-Nanometer Designs with Cadence Encounter Digital IC Design Platform

Cadence Selected by MIET to Ramp up Russian Startup Ecosystem

Cadence and Sun Extend Collaboration and Announce Broad Support for EDA Applications

December 2005

Intersymbol Deploys Cadence Encounter Platform in Mixed-Signal Flow to Cut Design Cycles, Die Area

Cadence Delivers Major Upgrade for SoC Verification in Incisive Enterprise Family

Cadence Delivers New RF Design Kit Targeting Customer Design Challenges in Wireless

New Cadence SoC Encounter GXL Addresses Customers' Nanometer Design Yield and Variation Challenges

Cadence Completes Digital Product Line Segmentation with Introduction of Encounter GXL Technologies

P.A. Semi Develops 65nm, Multicore Processor Family Using Cadence Synthesis and Implementation

New Cadence Encounter Conformal Low Power GXL Addresses Customer Verification Challenges

Cadence Extends Synthesis Technology Lead with New Encounter RTL Compiler GXL

November 2005

Cadence Introduces Incisive Enterprise, Linking Multiple Specialists and Languages

Initial Ballot to Make e Language an IEEE Standard Passes Overwhelmingly

Freescale and Cadence partner to innovate semiconductor product design

Hitachi Communication Technologies Chooses Cadence Incisive Enterprise Palladium II to Reduce Overall Verification Risks

MediaTek Successfully Adopts Cadence Design Constraint Solution

Cadence Supports STARC Technology to Improve Delay Test Quality

Cadence Validates Test and Diagnostic Flow with Agilent

Atmel Creates First Single-Chip DVD/CD SoC Using Cadence Encounter Test

October 2005

Cadence Commences Trading Under New Symbol 'CDNS'

Cadence Reports Q3 Revenue Up 12% Over Q3 2004

Cadence Advances Segmentation Strategy with 3 Tiers of Verification Products and Methodologies

Cadence Provides Powerful Low-Risk SystemVerilog Verification from Plan to Closure

Cadence Backs User Demand for Accelerating IEEE P1647 e Standardization

Cadence Announces Best Overall Paper Presented at CDNLive! Silicon Valley Conference

Cadence and UMC Sign Agreement to Streamline Wireless Design in the Fabless Market

Cadence Aligns Capabilities for Consumer and Mobile Applications to Support ARM's Cortex-A8 Processor

Toshiba Tapes Out First Universalarray Chip with Cadence Encounter

Silicon & Software Systems Completes 65nm Consumer Chip with Cadence Encounter

September 2005

Comit Systems Speeds Time to Market with Cadence Synthesis

Cadence Announces New Capabilities to Simplify and Accelerate PowerPC Design

ARM and Cadence Optimize Digital SOC Design Through Expanded Collaboration

New Cadence Product Segmentation and Technology Address Growth in Chip Complexity

New Cadence Physical Verification System Changes Physical Verification Paradigm

Cadence Delivers on First Milestone in Kits Strategy

ITRI Tapes Out Low-Power DVFS Test Chip with Cadence Encounter Synthesis and Implementation

Cadence Announces Support for Industry-Standard OpenAccess 2.2 Database

Elan Microelectronics Harnesses Cadence Encounter Conformal Custom Technology

Magnum Semiconductor Becomes 100th Customer for Cadence Encounter RTL Compiler

August 2005

Cadence Enables SensorDynamics to Reduce Design Cycles and Speed Successful Tapeout

HiSilicon Technologies Collaborates With Cadence and SMIC to Produce Communications Device

Latest Advances in Cadence IC Packaging Technology Further Tighten Design Cycle

Cray Accelerates Development of Next-Generation Supercomputer Using Cadence Virtuoso Layout Migrate and Engineering Services

Global Unichip Improves Quality of Silicon with Cadence Synthesis Technology

Fujitsu to Ship Initial Production Volumes of New Structured ASIC Built Using Cadence Encounter

July 2005

Cadence Announces Opening Keynote Speakers at First CDNLive! User Conference in Silicon Valley

Cadence Reports Q2 Revenue Up 12% Over Q2 2004

OrCAD Technology Enhancements from Cadence Improve Efficiency for Scalable PCB Design

Cadence Helps Sequans Achieve Early Time to Market with Wireless Broadband Chip Tapeout

Accent, ARM and Cadence Collaborate to Improve Low-Power Design

New Cadence Allegro PCB Design Technology Shortens Design Time and Strengthens Design Chain

Adoption of Cadence Encounter RTL Compiler Accelerates in Japan

Epson Doubles Productivity in LCD Controller Chip Tapeout with Encounter RTL Compiler

Cadence Completes Leadership Transition

June 2005

X Initiative Honors ATI and TSMC with Design-To-Manufacturing Catalyst Award

Essence Reduces Synthesizable Area by 30 Percent with Cadence Encounter RTL Compiler

Nethra Speeds Tapeout of Image Processor with Cadence Encounter RTL Compiler

Agere Adds Palladium II After Successful Rollout of TrueAdvantage Converged Access Solutions

Cadence Leads EDA Into New ERA of 'Enterprise VPA' Linking Design and Verification Specialists

ATI, Cadence and TSMC Produce Industry's First Fabless X Architecture Chip

Cadence� Encounter� Platform Now Available on 64-Bit Intel� Xeon� Processor-Based Systems

Cadence Supports TSMC Reference Flow 6.0 to Accelerate 65-Nanometer Design

Oki Develops Analog Blocks Five Times Faster with Cadence Technology

Virage Logic and Cadence Further Enable Low-Power Design

Cadence Delivers 50% Power Savings in Latest STARC Production Flow

May 2005

New Cadence PowerMeter Technology Enables Sighoff-quality Dynamic Power Rail Verification

Cadence, IBM, Chartered Continue Collaboration to Enable 90-nanometer Design Success

Ricoh Tapes Out 90nm Chip Early with Cadence Encounter RTL Compiler

Cadence and Faraday Announce Library Collaboration for Nanometer Design

New Cadence Incisive Formal Verifier Extends the Power of Formal Analysis to Designers' Desktops

April 2005

Cadence PCI Express Solution Passes PCI-SIG Compliance Testing

Cadence Completes Acquisition of Verisity

March 2005

Cadence Contribution to Accellera Boosts Efforts to Standardize IC Design Kits for Designers

Silicon Design Chain Collaboration Demonstrates Significant 90-nanometer Total Power reduction

Enhanced Signal Integrity Analysis Enables Cadence Customers Address Low-power Design Challenges

Latest OrCAD Technology from Cadence Strengthens Scalable PCB-level Design

Collaborative PCB Design Challenges Tackled by new Cadence Partitioning Technology

Cadence Delivers Industry's First Full-chip Test Technology

February 2005

Cadence and Virage Logic Collaborate to Deliver Timing and Signal Integrity Views to Enable Low-Power Design

Cadence and Verisity announce expiration of Hart-Scott-Rodino waiting period

GUC Tapes Out 7 Nanometer Designs with Cadence Encounter Technology

New Global Organization of Cadence Customers Created to Bolster Exchange of Ideas and Information

Silicon & Software Systems Successfully Tapes Out Multiple 90nm Designs with Cadence Encounter Platform

ATI Technologies Selects Cadence Palladium II for Verification of Advanced DTV Chips

Cadence Donates Technology to IEEE to Enhance SystemVerilog Usability

Cadence Allegro Package Designer Named as One of EDN's Hot 100 Products of 2004

Cadence, IBM and Rising Collaborate to Enable Leading-Edge SCDMA/GSM RF IC Transceiver

January 2005

Sanyo Achieves Production Design Success for Digital Consumer Product with Cadence Encounter RTL Compiler

Fujitsu Successfully Completes 66 Consecutive Designs with Cadence Encounter

Cadence Introduces New Mixed-signal and Radio Frequency Capabilities to Address Wireless Design Challenges

Cadence Meets Design Constraint Challenges with Enhanced Encounter Conformal Technology

Cadence Augments Verification Solution and Expertise Through Acquisition of Verisity

December 2004

Oki Tapes Out with New Cadence Synthesis Low-power Technology

Toshiba Supports Cadence Encounter RTL Compiler for ASIC Design Flow

NEC Implements Leading-Edge 90nm Vector Supercomputer Chipset with Cadence Encounter

Azul Implements High-Speed Chip with Cadence Encounter

Cadence Joins with IBM to Launch Power.org

November 2004

Cadence Design Systems Augments Executive Team and Announces New Assignments

Cadence Takes Formal Verification to Next Level with Conformal 5.0

Chartered and Cadence Qualify Fire & Ice QX for Leading-Edge Process Technologies

Media Advisory: Cadence Chief Technology Officer Ted Vucurevich Presents at 2004 IEE EDA Tools Forum

Cadence Sponsors Industry Forums

October 2004

Toshiba Implements Its Largest Semiconductor Design to Date with Cadence Digital IC Flow

Cadence and ARM Tackle Signal Integrity Issues for Foundry Program Partners with New Views

New Palladium II Extends Cadence Acceleration/Emulation Leadership

Cadence Introduces Industry's First Yield Diagnostics Tool

Cadence Announces Comprehensive Assertion-based Verification Solution

Magma and Cadence Establish Leading-edge Timing Model Standard

PalmChip Qualifies Cadence Encounter Synthesis for AcurX SoC Platform

New Scalable OrCAD Technology from Cadence Further Tightens PCB Design Process

Artisan and Cadence Collaborate to Optimize Low-Power Chip Design

September 2004

Renesas Technology Standardizes on Cadence MaskCompose to Reduce Mask-Marking Cycle Times and Costs

Cadence Sponsors Renovation of EDA Laboratory at Czech Technical University in Prague

Cadence Allegro System Interconnect Design Platform Customized for Use with Intel's PCB Design-In Kit

Cadence Incisive Conformal Technology Becomes Standardized Solution for Fujitsu Worldwide

UMC and Cadence Deliver Digital Reference Flow for Advanced Processes

August 2004

Shanghai Research Center for Integrated Circuit Design and Cadence Introduce New CPU/DSP Core-Based Methodology for SOC Chips

Cadence Accelerates Time to Market for Stretch

ATI Selects Cadence Incisive Palladium System for Verification of Complex Multimedia SoCs

Cadence Incisive Palladium System Cuts NVIDIA's Verification Time in Half

Cadence Virtuoso UltraSim Simulator Speeds Verification of TelASIC's Complex Mixed-signal Design

Cadence Announces New OrCAD Technology to Help Shorten PCB Design Cycles

Fujitsu Ties Global Partnership with Cadence to Create Advanced SoC Design Environments

Cadence Elects Michael J. Fister to its Board of Directors

July 2004

ATI Implements Award-winning Radeon X800 Series with Cadence Encounter

New Release of Cadence Allegro System Interconnect Design Platform Helps Increase PCB Engineer Productivity

Cadence Delivers Advanced Verification Environment for Palladium Acceleration/Emulation System

Atmel Adopts Cadence Virtuoso UltraSim FastSpice Simulator for Verifying Complex Mixed-signal Designs

Enhanced Cadence Virtuoso Platform Delivers Broader Capabilities to Speed Custom IC Design

June 2004

Cadence Announces PCB Industry's First High-Capacity Simulation Solution for Multi-Gigahertz Signal Design

Cadence Delivers New Allegro Design Workbench

TSMC and Cadence Tackle Low Power Challenges at 90 Nanometers and Below with New TSMC Reference Flow

Cadence and ASML Sign Multi-Year Business Agreement to Develop Advanced DFM Solutions

Cadence Announces First Encounter Global Physical Synthesis

Cadence Encounter Platform Supports Virage Logic Structured-ASIC Design Libraries

Cadence and CoWare Deliver Electronic System-Level (ESL) Design-for-Verification Flow

May 2004

Cadence is First EDA Company to Open Research & Development and Customer Support Center in Russia

CADENCE DESIGN SYSTEMS PROVIDES FREE ACTIVEPARTS ONLINE DATABASE FOR ORCAD CUSTOMERS

Cadence Delivers 90-Nanometer Reference Flow to Optimize Nanometer Design for IBM-Chartered Process Platform

T3G Selects Cadence Incisive Platform to Speed Time-to-Market for Mobile Phone Chipset in China

Aspex Semiconductor Uses Cadence Encounter Platform to Implement 130nm Linedancer Processor

Cadence Introduces NanoRoute Super-threaded Route Acceleration

Cadence Brings Timing to the Manufacturing Floor

Industry Leaders Drive Phased Implementation and Interoperability Testing of SystemVerilog Design and Assertion Constructs

Cadence Design Systems Names Michael J. Fister, Former Top Intel Executive, as President and CEO

Leading Tech Companies Adopt Cadence Incisive Platform to Reduce Verification Bottlenecks

April 2004

UMC and Cadence Deliver Analog Reference Flow for Mixed-Signal Designs

TSMC Qualifies Cadence Encounter RTL Compiler for Next-Generation Reference Flow

Toshiba Implements 8-Million-gate Networking Switch Using Cadence Encounter Digital IC Platform

Cadence to Acquire Neolinear

Cadence and MIPS Technologies Deliver Encounter Reference Methodology for Industry's Highest Performance 32-bit Core Family

March 2004

Agere Systems Uses Cadence Encounter RTL Compiler Synthesis for ASIC Customers

Procket Networks Standardizes on Cadence Encounter RTL Compiler for its Synthesis Tool of Choice

Motorola Implements 90nm Wireless Signal Processor Using Cadence Encounter Digital IC Design Platform

New Cadence Allegro Platform Delivers On-target, On-time, High-speed System Interconnect Design

Cadence Announces Agilent Technologies' Successful Implementation of a 90nm Digital Signal Processor Using the Cadence Encounter Digital IC Platform

Cadence Enhances Virtuoso Platform with New Chip Integration Solution for Fast, High-performance Custom Design

February 2004

Cadence Delivers Encounter RTL Compiler Ultra with Support for VHDL

Cadence and ARM Upgrade Quality of Silicon Results for ARM Partners with RTL Compiler Synthesis

January 2004

Cadence to Support 64-Bit Linux Computing Platforms Based on AMD64 Processors

Cadence Supports 64-Bit Intel Itanium 2-Based Platforms Running Linux

Cadence and 0-In Collaborate to Deliver Superior Assertion-Based Verification

Cadence to List Stock on Both NASDAQ AND NYSE

Cypress Semiconductor Corp. Adopts Cadence Fire & Ice QXC for 130 and 90 Nanometer Flows

Cadence Acquires Q Design Automation, Inc., Adds Process Migration to Virtuoso Custom Platform

December 2003

Cadence Design Systems Appoints Ping Chao to Lead Company's Design and Verification Business

Cadence Instrumental in Helping Motorola Tape out Its First Reconfigurable Compute Fabric Device

Faraday Adopts Cadence Encounter Platform for Structured ASIC Design

NEC Electronics and Cadence Announce Encounter Platform to Support NEC Electronics' ISSP Structured ASIC Platform

Cadence Fire & Ice QXC Verified for TSMC'S 90 Nanometer Technology

November 2003

Cadence Streamlines the PCB Design Flow with SPECCTRAQuest for Electrical Engineers

CADENCE MARKS 100TH TAPEOUT, GROWING INDUSTRY ACCEPTANCE OF ENCOUNTER PLATFORM�S NANOROUTE

CADENCE DESIGN SYSTEMS ENABLES ZORAN TO HIT AGRESSIVE DEADLINE AND SILICON AREA

Jan Willis to Head Industry Marketing for Cadence

October 2003

Renesas Technology Adopts Cadence Encounter Digital IC Design Platform's SignalStorm NDC as Sign-off Delay Calculator for Nanometer Designs

Cadence Encounter Platform Deployed By STMicroelectronics' Audio Division to Meet XM Radio Tape-out Demands

Cadence Delivers Industry's First Complete IC Package and PCB Design Flow to Run on Linux

Cadence Embraces SystemVerilog

Cadence Solutions and Services Helps Speed SensorDynamics' Complex Micro Sensor Applications

Cadence Introduces Industry's First Integrated IC Packaging Design and Signal Integrity Solution

September 2003

Cadence Unveils Industry's Most Comprehensive Test Solution to Link Design and Manufacturing

Cadence and dSPACE to Collaborate on Distributed Model-Based Design Flow for Automotive Applications

New Cadence Encounter Platform Release Accelerates High-End Digital IC Design

Cadence and Chartered Team to Deliver Solutions for 90-nanometer IC Design

ARM and Cadence Enable ARM Core-Based Designs Through the Silicon Design Chain

Cadence Announces Availability of Design-in Kit for Intel IXP2800 Network Processor

New Cadence Virtuoso Platform Delivers Fast, Silicon-accurate Custom Design

Cadence Ships OrCAD 10.0 Release, Increasing Productivity for Windows-Based PCB Designers

Cadence and CoWare Alliance to Provide Unified System-to-Silicon Design Solution

August 2003

IPCore and Cadence Collaborate to Launch Advanced Design Methodology Based on CSMC Process

Cadence Delivers Most Accurate Cell-Based Extractor for Nanometer-Scale Designs

Cadence Enables Aspex Technology to Meet Market Demands for Ultra-High-Performance Processors

July 2003

Cadence Announces Industry's First Complete Environment for Gigabit-Speed PCB Systems Design

Cadence Cuts Matsushita's Verification Runtime to Minutes

Cadence Signs Definitive Agreement to Acquire Verplex

June 2003

Cadence services instrumental to TransChip in developing single-chip imaging camera solution

Cadence selected by Artimi to speed development of its UWB transceiver devices

Tower Semiconductor Releases 0.18 and 0.35 Micron Process Design Kits

Metalink adopts Cadence Encounter for high-performance broadband access chipsets

Cadence Qualifies Reference Flow for IBM Nanometer Technology

Cadence Enables Open Interoperability for Next-Generation IEEE Verilog

TSMC Employs Cadence Encounter Platform in New TSMC Reference Flow 4.0

May 2003

Cadence Design Systems Presents Demonstrations at DAC Showcasing the Latest Electronic Design Automation Technologies for June 2-4 (Mon. - Wed.)Design Automation Conference 2003

Cadence Announces Aptivia Parallel Characterization Option

Cadence Takes on Mixed-Signal Design with Enhanced UltraSim Fast-SPICE Simulator

CADENCE SERVICES INSTRUMENTAL IN DELIVERING NANOTRON�s GROUNDBREAKING nanoNET TRX RF CHIP DESIGN

Cadence First Encounter Selected to Enable Nanometer SoC Design in Infineon's Inway Design Environment

Industry Leaders Select Cadence Incisive Verification

Cadence, MatrixOne and IBM Collaborate to Deliver Product Design Solutions for the Global Electronics Industry

Cadence and MatrixOne to Create PLM Solutions for Global Electronics Industry

OpenAccess Enables New Cadence Virtuoso Chip Editor to Speed Chip Finishing Up to 10x or More

AsusTeK Selects Cadence SPECCTRAQuest For High-Speed PCB System Development

Cadence Enables Teradiant Networks to Expedite Development of New Network Processing Chipset

Cadence Acquires K2 Technologies

April 2003

Cadence SoC Encounter Wins EDN Magazine Innovation of the Year Award

Cadence Teams with TeraChip to Deliver World's First 160Gbps Switch Fabric Chip

Cadence Successfully Ports Design Software to 64-Bit Linux Operating System for AMD Opteron Processor and AMD64 Architecture

Cadence Optimizes Design Chain for Xilinx Customers Using the 90nm Spartan-3 FPGA Platform

Agere Systems and Cadence Design Systems Donate Chartreuse-II to VSI Alliance

Get2Chip Acquisition Empowers Cadence with Industry's Best Nanometer-Scale Synthesis Technology

March 2003

Cadence Named One of ''America's Most Admired Companies''

Wintegra Deploys Cadence Encounter Platform for Market Leading Access Packet Processor Designs

Cadence Automates Wirebonding Design for Stacked-Die Packages

Cadence Introduces Technology Key to Multigigabit Serial Interface Design in PCB Systems

ARM and Cadence Establish New Five-Year Agreement Targeting Design Chain Optimization

Cadence Enhances Leading Nanometer Encounter Signal Integrity Solution

Cadence Joins the FlexRay Consortium

February 2003

New Cadence Incisive� Verification Platform Compresses Overall Verification of Nanometer-scale Designs by Up to 50 Percent

Xilinx and Cadence Solution Speeds Multi-Gigabit Designs for System Companies

Cadence First Encounter Selected by ST for 90 Nanometer System-on-Chip Design

January 2003

Cadence and ATI Team to Form Broad Reaching Partnership

IBM and Cadence Use Supercomputing Power of Linux in Leading Electronic Design Solutions

Cadence Acquires Celestry, Further Strengthens Fab Relationships

Cadence and TSMC Team to Accelerate Time-to-Volume for Nanometer Design; Cadence is First Full-Line Distributor of TSMC-Developed Libraries

November 2002

Physical synthesis customers NEC and AMCC adopt Cadence NanoRoute Ultra for nanometer design

Fujitsu deploys Cadence nanometer analysis technology to achieve timing closure for high-end ASIC designs

Cadence v. Avant! Litigation settled

July 2002

Toumaz Standardizes On Cadence Tools And Services For New Class Of Ultra-Low Power Semiconductors

Cadence Reports Second Quarter Results

June 2002

Cadence Receives Prestigious IEEE Award For Industry Leadership In Innovation

Cadence And Agilent Technologies Enable Wireless, Wireline Industries To Speed IC Design With First Joint Product

New Cadence 5.0 Custom IC Software Release Expands Lead in Growing Digital/Mixed-Signal Market

Motorola Chooses Cadence AMS Designer For Large Next-Generation Mixed-Signal SOC Simulation

Motorola Chooses Cadence AMS Designer For Large Next-Generation Mixed-Signal SoC Simulation

Quickturn Announces New Palladium Configurations And Software Supporting Designs Up To 128 Million Gates

May 2002

Cadence SP&R Upgrade Speeds Design Of Large Chips

April 2002

Cadence Expands Technology Leadership At 0.13-Micron-And-Below With Acquisition Of Simplex

Cadence Reports First Quarter Results

March 2002

New Cadence PCB Design Release Analyzes Differential Interconnect Across Chip, Package And Board

New Cadence Orcad Unison Suite For Windows-Based PCB Design Targets Individual Productivity

Plato Design Systems Acquisition Complements Powerful IC Implementation Solution From Cadence

DATE 2002: Cadence Offers NC-Sim Plus Front-End Logic Design And Verification Package

DATE 2002: Cadence Adds Major Enhancements To Its Market Leading Signal Processing Worksystem

DATE 2002: Major Cadence Customers Adopt New SoC Encounter For 0.13-Micron Hierarchical IC Design

February 2002

ChipPAC Adopts Cadence IC Packaging Design Technology For Use Worldwide

Openaccess Coalition Releases Source Code Roadmap And Announces Openconnect Program For Design Technology Interoperability

January 2002

Cadence Reports Record 2001 Results

Cadence To Offer Simplex Extraction Technology

Silicon Perspective First Encounter From Cadence Supports IBM ASIC Physical Handoff Flow

Gemplus Selects Cadence Design Flow For Complex IC Design

December 2001

Quickturn Palladium Design Verification System Purchased By Multilink Technology Corporation To Speed Simulation Of Selected Networking Designs

November 2001

Cadence Selected By STMicroelectronics For Its Automotive And Digital Consumer Platforms Co-Design Environments

Silicon Perspective Acquisition Adds Breakthrough Hierarchical Capabilities To Cadence SoC Design Technology

October 2001

DSP Pioneer Siroyan Selects Quickturn For Emulation Solution To Speed Design Cycle

August 2001

Quickturn's Cobalt Ultra Breaks The 100-Million-Gate Capacity Barrier

Cadence Offers Free Workshop on Testbench Development in C++

Quickturn Extends �Quickstart� Program To Provide Upgrade Path For Emulation Customers

July 2001

Cadence Enables Motorola With Leading Analog/Mixed-Signal Design Solution

Cadence Awarded $182 Million Plus Interest In Avant! Criminal Restitution Proceeding

Quickturn Emulation System Selected By ARM To Verify New RISC Processor Core

Cadence Expands Relationship With Hitachi By Renewing License Of SP&R Technologies

Cadence Announces Strong Second Quarter Results

Cadence Announces Sign-Off Support From LSI Logic For Cadence SP&R In Asic Design Flows

June 2001

Quickturn Announces Palladium, The Most Advanced Simulation Acceleration And In-Circuit Emulation System

Cadence Strikes Three-Year Deal With Stepmind

Cadence Defines Vision To Address Design Chain Convergence Challenges

March 2001

Robert Bosch Gmbh Selects Quickturn For Next-Generation In-Circuit Fault Emulation Projects

Cadence Partnerships Set Pace For Analog/Mixed-Signal Chip Design

Cadence Advances Its PCB Design Environment

Cadence And Agere Announce Strategic Alliance To Develop Chip I/O Planning Capability

Quickturn, Philips Semiconductors, And The University Of Rostock Announce Joint Technology Partnership Program

Cadence And TSMC Collaborate To Distribute Design Kits For Baseband And RF Foundry Silicon

Cadence And Philips Semiconductors Agree To Expanded Licence Renewal Contract

February 2001

Cadence Extends SOC Technology Leadership With New Integration Ensemble And Unveils Superchip Initiative

Quickturn Ships Record Number Of Emulation Gates Worldwide With The MercuryPlus In-Circuit Emulation System, Featuring Custom FPGAs

Cadence Selected By Stmicroelectronics To Support System Design Based On New St100 Dsp

January 2001

Cadence Constraint Manager Elevates Rules-driven High-speed PCB Design to Next Level

Cadence Announces Record Fourth Quarter

Cadence Enables Fabless Company To Accelerate Availability Of Advanced XDSL Solutions

Cadence SP&R Design Tools Used By Fujitsu To Tape-Out 1.6 Million Gate, 266 Mhz Embedded Microprocessor

Cadence Extends SOC Leadership With Acquisition Of CadMOS Design Technology

November 2000

Cadence And Transim To Provide Online PSpice And IC Component Evaluation

October 2000

Cadence Assura Solution Targets Chip Designers In High-Growth Communications Market Segments

Cadence To Ship New Allegro And Specctra Routing Enhancements With Full Specctra Support For Mentor Board Station Users

Cadence Announces Third Quarter 2000 Results

Cadence Announces That Texas Instruments Expands Licence Agreement

Cadence SP&R Solution Used By Geocast Network Systems To Tape-Out Data Decoder

September 2000

Cadence VCC 2.0 Delivers New Modeling Capabilities For Platform-Based Design, Optimizing Time-To-Market And Soc Design Chain Interaction

Cadence Envisia Physically Knowledgeable Synthesis Selected By Ericsson Microwave Systems AB

Tality Takes Lead In ARM Core-Based System-On-Chip Design

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